Jeannie Lau is a parasitic extraction expert and ASIC LVS expert (layout-versus-schematic verification), with over a decade of specialist experience built across roles at GLOBALFOUNDRIES, Intel, and Primarius Technologies. She specializes in circuit analysis, RC extraction, and static timing analysis (STA) across StarRC, xRC, and Quantus/QRC flows.
As an ASIC EDA flow expert, Jeannie has developed and qualified custom extraction and LVS flows against foundry PDKs down to 14nm and 10nm process nodes, working across ITF/ICT/MIPT techfile development and multi-vendor extraction qualification (StarRC, xRC, Quantus). She holds an Altera Innovator Award for her work resolving capacitive shielding issues affecting signal integrity.
Her background spans debugging complex extraction problems — opens, shorts, large capacitance, and PrimeTime back-annotation errors — and building Perl, Tcl, and Python-based automation for ASIC and custom extraction flows. At LogikHaus, she leads analog design and verification at the PCB level, alongside hardware debug and embedded system verification.